The present invention relates to a control circuit that controls an internal circuit based on an external operation request and an internal operation request and to a semiconductor memory device including such control circuit.
Nowadays, a dynamic random access memory (DRAM), which has a large memory capacity, is used in electronic information devices. A DRAM is provided with a self-refresh function that refreshes cell data of a memory cell based on a counter operation of an internal circuit. A DRAM provided with the self-refresh function does not require an external refresh manipulation. Thus, power consumption is reduced and the designing of a circuit about the DRAM is facilitated.
FIG. 1 is a block circuit diagram illustrating a prior art input circuit section of a DRAM 100, which is provided with a self-refresh function.
The DRAM 100 receives an output enable signal /OE, a write enable signal /WE, and a chip enable signal /CE1, which are all control signals. The signals /OE, /WE, /CE1 are provided to filters 14, 15, 16 via input buffers 11, 12, 13, respectively. Each of the input buffers 11-13 is an input initial stage circuit that coverts an input signal to a signal having a level corresponding to an internal voltage of a device and is, for example, a CMOS inverter circuit or a C/M (current mirror) differential amplification circuit.
Each of the filters 14-16 eliminates noise components, such as a glitch, from the signal provided by an external circuit. The data of the DRAM is held using a charge holding technique. When an undetermined noise is included in the input signal, the level of a word line is shifted in a state in which the internal operation of a device has not yet been determined. The elimination of a noise component prevents the data of a memory cell from being damaged.
The noise status of each signal changes in accordance with a system board, in which the DRAM 100 is used. Thus, the filters 14-16 are normally designed to resist noises that may be produced in the worst cases. Accordingly, the set value of the filters 14-16 normally restricts the access time for reading and writing data. Thus, the set value significantly affects the access time.
Output signals oeb5z, web5z, clb5z of the filters 14, 15, 16 are provided to first, second, and third control transition detectors (CTDs) 17, 18, 19 and to a control data decoder (CTLDEC) 20. The transition detectors 17, 18, 19 each detect the transition of the status of the input signal and generates detection signals oerex, werex, cerex.
The control decoder 20 decodes commands based on the voltage level (high level or low level) of the external control signals (in this example, the chip enable signal /CE1, the output enable signal /OE, and the write enable signal /WE). The commands include, for example, a write command and a read command. The control decoder 20 provides a control signal (e.g., a write control signal wrz based on a write command or a read control signal rdz based on a read command), which is based on the decoded command to an activation pulse signal generator (ACTPGEN) 21.
An external address signal Add is provided to an address transition detector (ATD) 24 via an input buffer 22 and a filter 23. The address transition detector 24 detects the transition of an external address signal Add (e.g., the change in the lowermost bit A less than 0 greater than  of the external address signal Add) and generates a detection signal adrex.
The detection signals oerex, werex, cerex, adrex of the respective transition detectors 17, 18, 19 and the detection signal adrex of the address transition detector 24 are provided to an address transition detection signal (ATDS) generator (ATDGEN) 25.
The ATDS generator 25 performs a logical operation on the detection signals oerex, werex, cerex, adrex and generates an activation signal atdpz based on the finally provided control signals /OE, /WE, /CE1 and the external address signal Add. The activation signal atdpz is provided to an external active latch generator (EALGEN) 26 and a refresh controller (REFCTL) 27.
The external active latch generator 26 generates a main signal mpealz, which activates a device based on the activation signal atdpz, and provides the main signal mpealz to the activation pulse signal generator 21.
The activation pulse signal generator 21 generates a write signal wrtz, a read signal redz, and an activation pulse signal actpz based on the control signals wrz, rdz from the control decoder 20 and the main signal mpealz. The activation pulse signal actpz is provided to a row address generator (RASGEN) 28. The activation pulse signal actpz is a signal that activates a row circuit, which controls word lines connected to a memory cell or a sense amp connected to bit lines, and a column circuit, which controls column gates connected to a data bus.
The refresh controller 27 is a so-called arbiter. The refresh controller 27 determines whether to select (give priority to) an internal refresh request (self-refresh request signal srtz) or an access request (activation signal atdpz) from an external device and generates a determination signal refz based on the determination. The determination signal refz is provided to the row address generator 28.
The row address generator 28 generates a base signal rasz of the word line selection signal based on the determination signal refz and the activation pulse signal actpz. When the refresh controller 27 selects an internal refresh request, the word line corresponding to the refresh address is activated based on the base signal rasz. When the external access request is selected, the word line corresponding to the external address signal Add is activated based on the base signal rasz. The refresh address is generated by an address counter (not shown).
The operation of the DRAM 100 will now be discussed.
FIG. 2 is a waveform chart taken when responding to an access request from an external device.
When the chip enable signal /CE1 goes low, the detection signals oerex, werex, cerex of the respective transition detectors 17, 18, 19 are output. Then, the ATDS generator 25 generates the activation signal atdpz. The main signal mpealz is generated based on the activation signal atdpz, and the activation pulse signal actpz is generated based on the main signal mpealz.
When responding to an external access request, the self-refresh request signal srtz is low. Thus, the determination signal refz remains unchanged (low level). The activation pulse signal generator 21 generates the activation pulse signal actpz and the write signal wrtz or the read signal redz based on the main signal mpealz from the external active latch generator 26 and the control signals wrz, rdz from the control decoder 20. The write signal wrtz indicates the write mode, and the read signal redz indicates the read mode. The level of the control signals (/WE, /OE) determines which one of the write signal wrtz and the read signal redz is to be generated.
The row address generator 28 generates the base signal rasz, which selects the word lines, based on the activation pulse signal actpz. Since the circuit responding to the base signal rasz does not have a refresh request, the word line corresponding to the external address signal Add is selected.
FIG. 3 is a waveform chart taken when the refresh request and the external access request overlap each other and the refresh request is selected.
When the refresh request is selected, the refresh controller 27 compares the activation signal atdpz and the internal refresh request signal srtz. If the refresh request signal srtz is earlier than the activation signal atdpz, the refresh controller 27 outputs the determination signal refz at a high level. Thus, the row address generator 28 gives priority to the internal refresh request and generates the base signal rasz to activate the word line corresponding to the internal refresh address.
Then, when the refresh operation is completed, the row address generator 28 generates the base signal rasz based on the activation pulse signal actpz. This activates the word line corresponding to the external address signal Add.
Accordingly, when priority is given to the internal refresh operation, the refresh controller 27 generates the base signal rasz, which activates the word line selected in correspondence with the external address signal Add.
FIG. 4 is a waveform chart taken when the refresh request and the external access request overlap each other and the external access request is selected.
When the refresh controller 27 determines that the refresh request signal srtz is delayed from the activation signal atdpz, the refresh controller 27 outputs the determination signal refz at a low level. Thus, the row address generator 28 gives priority to the external access request and generates the base signal rasz to activate the word line corresponding to the external address signal Add.
Then, when the external access operation is completed, the row address generator 28 generates the base signal rasz based on the refresh request signal srtz. This activates the word line corresponding to the internal refresh address.
In this manner, a memory (DRAM), which automatically performs a refresh operation in a device, basically gives priority to the internal refresh operation to hold the information of a memory cell when the internal refresh request and the access request from the external device overlap each other. This is because the internal refresh request timing (refresh interval) is determined by the memory holding capacity (data holding time) of the memory cell.
Accordingly, when the internal refresh request and the access request from the external device overlap each other, the response time of the device relative to the external access request is the sum of the normal time required for the external device to perform an access operation and the time required to perform the internal refresh operation. Accordingly, the time required by the device to respond to the external access request is about two times longer than when the external access request and the internal refresh request do not overlap each other. The increase in the response time makes it difficult to increase the speed of the device.
It is an object of the present invention to provide a control circuit that increases the speed of a device to respond to a control request from an external device when an internal control request of the device overlaps the external control request and to provide a semiconductor device including such control circuit.
To achieve the above object, the present invention provides a control circuit connected to an internal circuit of a semiconductor device. The control circuit generates a main signal based on a first control signal and a second control signal to control the internal circuit. The control circuit includes a first signal processing unit for receiving the first control signal and generating a first processed signal from the first control signal. The first signal processing unit includes a filter for filtering the first control signal. A second signal processing unit receives the first control signal and generates a second processed signal. An arbiter receives the second processed signal and the second control signal, determines which one of the second processed signal and the second control signal is to be given priority, and generates a determination signal based on the determination. A main signal generator is connected to the first signal processing circuit and the arbiter to generate the main signal from the determination signal or the first processed signal in accordance with the determination signal.
A further perspective of the present invention is a semiconductor memory device for performing a self-refresh operation based on an internal refresh request signal. The device has a first detection unit including a filter for receiving an external access request signal and eliminating a noise component from the external access request signal. The first detection unit detects transition of an output signal of the filter and generates a first detection signal based on the detection. A second detection unit receives the external access request signal, detects transition of the external access request signal, and generates a second detection signal based on the detection. An arbiter is connected to the second detection unit to generate a determination signal based on the second detection signal and the internal refresh request signal. The determination signal indicates which one of the external access request and the internal refresh request is to be given priority. A main signal generator is connected to the first detection unit and the arbiter to generate a main signal from the first detection signal or the determination signal in accordance with the determination signal to control the internal circuit of the device.
A further perspective of the present invention is a semiconductor memory device for performing a self-refresh operation based on an internal refresh request signal. The device has a first detection unit including a first filter for receiving an external access request signal and eliminating a noise component from the external access request signal. The first detection unit detects transition of an output signal of the first filter and generates a first detection signal based on the detection. A second detection unit receives the external access request signal, detects transition of the external access request signal, and generates a second detection signal based on the detection. A first address transition detection unit includes a second filter for receiving an external address signal and eliminating a noise component from the external address signal. The first address transition detection unit detects transition of an output signal of the second filter and generates a first address detection signal based on the detection. A second address transition detection unit receives the external address signal, detects transition of the external address signal, and generates a second address detection signal based on the detection. A first signal synthesizing circuit is connected to the first detection unit and the first address transition detection unit to perform a logical operation with the first detection signal and the first address detection signal and generate a first synthesizing signal based on a result of the logical operation. A second signal synthesizing circuit is connected to the second detection unit and the second address transition detection unit to perform a logical operation with the second detection signal and the second address detection signal and generate a second synthesizing signal based on a result of the logical operation. An arbiter is connected to the second signal synthesizing circuit to perform a logical operation with the second synthesizing signal and the internal refresh request signal and generate a determination signal based on a result of the logical operation. The determination signal indicates which one of the external access request and the internal refresh request is to be given priority. A main signal generator is connected to the first signal synthesizing circuit and the arbiter to generate a main signal from the first detection signal or the determination signal in accordance with the determination signal to control the internal circuit of the device.